Conventional programmable logic modules such as processors run programs which are loaded from a memory. These memories may be in the form of discrete modules (for example a hard disk, a memory chip), or may be integrated in the processor. One known example of the former is the known IBM-compatible PCs, and an example of the latter is so-called flash microprocessors. The software to be run is stored in the form of command words as a machine command in the memory. The command words are loaded, analyzed and carried out in a processing unit. The processing of a single command word initiates a large number of individual actions in the logic unit.
One critical characterizing feature of conventional programmable logic modules is that the processing unit is reprogrammed for a number of clock cycles by each new command word. The information relating to the previous command word is overwritten in the processing unit, apart from register contents. The processing unit in modern microprocessors is highly complex in design, owing to the large number of possible operations. More than 30 million transistors are required for fewer than 500 possible command words, which leads to a correspondingly high power consumption since each transistor consumes energy even when it is not being used and is in the “waiting state”. It has already been proposed that the operating voltage be adapted, that is to say reduced, in order to save energy. The clock frequency can likewise be reduced, although this reduces the overall performance of the logic unit.
The complexity for the design, manufacture and testing of these transistors is immense. Once the functionality has been designed, it cannot be changed. Only one task can be processed at a specific time.
Particularly when running through program loops, only a small portion of the processor is active. Most applications contain a large number of program loops, with each loop containing only a relatively small number of commands embedded in the loop. These may be counting loops, for example in order to count the number of rinsing processes in a washing machine. Conditional loops are likewise very frequent, in which the number of repetitions is not known when the loop is entered, since the loop is left as a function of a result. If the event does not occur, the previous commands in the loop are repeated.
Known digital logic units, in particular computers with microprocessors, are based on the concept of the von-Neumann computer. The central processing unit, that is to say the computer core, comprises the major components formed by the main memory, the control unit and the processing unit (arithmetic unit). The main memory stores command words (program data) and processing data (operand words), and makes them available on request. The main memory also holds intermediate results and final results from the processing. Main memories may be formed by volatile or non-volatile memories. The control unit organizes the sequence in which command words are processed. It requests command words from the main memory, and causes the command word to be carried out in the processing unit. It analyzes command words, and causes processing data to be supplied to the processing unit. The processing unit carries out the operation on the processing data, and supplies the results to the main memory. The processing unit contains a microprogram for each operation, which releases the required transmission lines. The processing unit is set by the control unit for the respective operation, that is to say for the command to be processed. This central processing unit has associated peripherals, which may be the abovementioned external memories, input and output appliances. The described main components of the central processing unit may be physically separated, but they are generally on a common processor chip with a cache, or, for example, on an embedded ROM.
Particularly in the case of frequently recurring actions, for example when running through program loops, the known digital logic units have the disadvantage that command words are loaded and carried out which were actually available a number of processor clock cycles previously in a command register. One example of a loop such as this is a keyboard check. When no key is depressed, all the loop commands are repeated at a short interval, in which case the command words have to be reloaded on each occasion, as if they were completely new. The vast majority of the processor is not required during this waiting time, but it cannot carry out any other tasks during this time.
The utilization level of a logic unit such as this is extremely poor since less than one thousand of the available hardware is used. The majority of the chip area remains unused, but power must nevertheless be supplied continuously for operation.
The matching of processors to different circumstances has already been implemented at a low complexity level. One example of this is the switching of memory banks for a processor, which contain different programs. Memory banks which are not in use at any given time can be changed. This technique is referred to as IAP (in application programming). The improvement that is achieved by this measure is comparatively minor, since nothing to do with the processor hardware has been changed, but only the programs to be run being loaded at the same time as other processes.
Programmable logic modules (PLD) are frequently used for less complex tasks. Logic modules such as these are known, for example, from U.S. Pat. No. 4,870,302 or from the publication “Ranmuthu, I. W., et al.; Magneto-resistive elements—An Alternative to Floating Gate Technology; In: Proceedings of the Midwest Symposiums on Circuits and Systems, 1992, pages 134–136 vol. 1”. The entire application program in logic modules such as these is translated to suitable commands in a specific compiler (so-called fitter). The PLD is defined with this program data only once, generally on booting up: a program is read from a program memory, and configurable areas are configured. The configurable areas have the following characteristics: they either define links between predetermined points (routing areas) or process logic input signals to form logic output signals (logic cell areas) However, if connections are required which differ from the technical PLD presets implemented by the manufacturer, two or more connection blocks must be cascaded, and this results in increases in the delay times and in throughput delays. In consequence, the actual speed at which the application program is run cannot be predicted. In many cases, adaptations are required in the program in order, for example, to make it possible to achieve a minimum speed requirement or synchronization of signals in a PLD. If characteristics other than those available are required while processing logic signals (for example a greater bit length), then they must likewise be cascaded. The linking areas in the PLD thus occupy a larger area than the logic areas. Despite the configurability of the modules, the flexibility for different tasks is thus low. Thus, in general, a different chip with a different chip architecture is chosen for practical problems, whose resources are better matched to the problem (for example bit length, throughput delay requirements).
The architecture concept of the PLDs provides for the programming information to be distributed by the fitter to a large number of identical logic cells on the PLD chip. These are linked by a large number of identical routing areas. The programming information is thus distributed over the area. The configurability of the PLDs is restricted to a small number of configurable parameters, which are permanently set on booting up. In this case, two memories are required: an external boot memory chip (discrete chip, for example an EEPROM 113 in U.S. Pat. No. 4,870,302) and internal memory cells distributed over an area (for example as shown in FIGS. 3a and 10a in U.S. Pat. No. 4,870,302 of FIG. 5 in the publication from Ranmuthu et al. After booting up, the local memory cells contain the information for the links and for the logic functions for the cells. The area and line loss efficiency of the distributed memory cells is approximately two orders of magnitude poorer than that of discrete memory chips of the same performance. However, if less performance is required by the application program than that provided by the chip, then the unused areas likewise unavoidably result in power losses. Typical utilization levels of the resources of PLDs are about 30% to 70%. Only small proportions of them are actively involved in the processing of logic information at any given time.